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Support Syntax Highlighting for Verilog and VHDL

Closed Support Syntax Highlighting for Verilog and VHDL
github/fork/manuelgutierrezsigasi/sigasi/support-hdl-languages into main
Closed Administrator requested to merge github/fork/manuelgutierrezsigasi/sigasi/support-hdl-languages into main

Created by: manuelgutierrezsigasi

cc @slimsag resolves https://github.com/sourcegraph/sourcegraph/issues/28259

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